The invention relates to basic input output systems and computer reset methods, in particular, to a rapid reset method that only resets the Central Processing Unit.
Central Processing Units (CPU) often need to reset. For example, when a frequency ratio is changed, or when the power state is restored from a suspend mode to a normal mode, a CPU reset is required.
FIG. 1 shows a conventional computer system architecture and signal flows thereof. The computer system 100 comprises a processor 102, a Northbridge 104, a Southbridge 106, and a Read Only Memory (ROM) device 108. The bus for the Northbridge 104 and Southbridge 106, can be Peripheral Connection Interface (PCI), or specific standards such as VIA® V-Link or Intel® ICH. The Northbridge 104 couples to the processor 102 via Front Side Bus (FSB), to memory devices (not shown) via a memory bus, and to graphic units (not shown) via Accelerated Graphic Ports (AGP). Conventionally, when the processor 102 requires a reset, the Northbridge 104 cannot actively perform CPU reset. Conversely, the Southbridge 106 must deliver a system reset signal PCI_RST#, to completely reset the computer system, thereby triggering the Northbridge 104 to deliver the CPU reset signal CPU_RST# to the processor 102. As shown in FIG. 1, the system reset signal PCI_RST# can be activated by a trigger 110, or by Basic Input Output System (BIOS) programmed in the computer system 100. The system reset signal PCI_RST# is delivered to units coupling to the PCI bus, and to the Northbridge 104 via the V-Link bus. When the Northbridge 104 receives the system reset signal PCI_RST#, corresponding reset signals RST# are individually generated by the Northbridge 104, and delivered to memory devices and graphic units respectively. Simultaneously, a CPU reset signal CPU_RST# is generated and delivered to the processor 102 via the Front Side Bus (FSB). Therefore the only way to reset the processor 102, is to completely reset the computer system 100.
In this method, however, the Northbridge 104 and Southbridge 106 are also reset, and data stored in the registers of the Northbridge 104 are lost, which is undesirable. Unrecoverable problems may occur when the computer system 100 returns from a power saving mode. Thus an initialization procedure is required to help the computer system 100 return to normal operation, increasing implementation complexity and cost.